View TLE638907_5040470.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Step-Down DC/DC Controller
TLE 6389
1 1.1 * * * * * * * * * * * * * * *
1)
Overview Features
Input voltage range from < 5V up to 60V Output voltage: 5V fixed or adjustable (7V to 15V) Output voltage accuracy: 3% Output current up to 2.3A 100% maximum duty cycle Less than 120A quiescent current at low loads1) 2A max. shutdown current at device off (TLE 6389-2 GV) Fixed 360kHz switching frequency Frequency synchronization input for external clocks Current Mode control scheme Integrated output under voltage Reset circuit On chip low battery detector (on chip comparator) Automotive temperature range -40C to 150 C Green Product (RoHS compliant) AEC qualified
dependend on external components
P DSO 14 3 8 9 11 1
VIN
RSENSE= 47m
M1
L1 = 47 H
V OUT IOUT
C IN1 = 100 F
C BDS= 220 nF
11 BDS VS 7 SI SI_GND 6 14 CS 12 GDRV
D1
COUT = 100 F M1: Infineon BSO613SPV Infineon BSP613P D1: Motorola MBRD360 L1: EPCOS B82479-A1473-M Coilcraft DO3340P-473 CIN1 : Electrolythic CIN2 : Ceramic COUT: Low ESR Tantalum
13
RSI1= 400k RSI2= 100k
CIN2 = 220nF
TLE6389-3 GV50
SI_ENABLE 1 ON OFF SYNC 5 GND 4
2 3 FB VOUT 9 SO 8 COMP RO 10
2.2nF 680
Type TLE 6389-2 GV TLE 6389-2 GV50 TLE 6389-3 GV50
Datasheet Rev. 2.1
Package PG-DSO-14-1 PG-DSO-14-1 PG-DSO-14-1
1
Description adjustable 5V, RO-Hysteresis << 5V, RO-Hysteresis 1V
2007-08-13
TLE 6389
1.2
Short functional description
The TLE 6389 step-down DC-DC switching controllers provide high efficiency over loads ranging from 1mA up to 2.5A. A unique PWM/PFM control scheme operates with up to a 100% duty cycle, resulting in very low dropout voltage. This control scheme eliminates minimum load requirements and reduces the supply current under light loads to 120A, depending on dimensioning of external components. In addition the adjustable version TLE6389-2 GV can be shut down via the Enable input reducing the input current to <2A. The TLE 6389 step-down controllers drive an external P-channel MOSFET, allowing design flexibility for applications up to 12.5W of output power. A high switching frequency and operation in continuous-conduction mode allow the use of tiny surfacemount inductors. Output capacitor requirements are also reduced, minimizing PC board area and system costs. The output voltage is preset at 5V (TLE6389-2 GV50 and TLE6389-3 GV50) and adjustable for the TLE6389-2 GV. The version TLE6389-2 GV50 features a reset function with a threshold between 4.5V and 4.8V, including a small hysteresis of typ. 50mV. In the version TLE6389-3 GV50 the device incorporates a reset with a typ. 1V hysteresis. Input voltages of all TLE 6389 can be up to 60V.
1.3
Pin Configuration (top view)
ENABLE / SI_ENABLE FB VOUT GND SYNC SI_GND SI
1 2 3 4 5 6 7
14 CS 13 VS 12 GDRV
P-D-SO-14
11 BDS 10 RO 9 8 SO COMP
Datasheet Rev. 2.1
2
2007-08-13
TLE 6389
1.4
Basic block diagram
VS
ENA BLE
SI
SIGND
VOUT
BDS
Internal Power Supply and Biasing
Battery Sense and Undervoltage Reset
RO
SO
FB
PWM / PFM Regulator
Driver
G DRV
CS
COMP
Voltage Reference Block
Clock generator
SYNC
TLE 6389GV
GND
Datasheet Rev. 2.1
3
2007-08-13
TLE 6389
1.5
Pin No 1
Pin Definitions and Functions
Symbol Function
ENABLE Active-High enable input (only at adjustable version, TLE6389-2 GV) for the device. The device is shut down when ENABLE is driven low. In this shut downmode the reference, the output and the external MOSFET are turned off. Connect to logic high for normal operation. SI_ENA BLE Active-High enable input (only at 5V version, TLE6389-2 GV50 and TLE6389-3 GV50) for SI_GND input. SI_GND is switched to high impedance when SI_ENABLE is low. High level at SI_ENABLE connects SI_GND to GND with low impedance. SO is undefined when SI_ENABLE is low. Feedback input. 1. For adjustable version (-2GV) connect this pin to an external voltage divider from the output to GND (see the determining the output voltage, application section). 2. At the 5V fixed output voltage version (-3GV50 and -2GV50) the FB is connected internally to an on-chip voltage divider. It does not have to be connected externally to the output. Buck output voltage input. Input for the internal supply. Connect always to the output of the buck converter (output capacitor). Ground connection. Analog signal ground. Input for external frequency synchronization. An external clock signal connected to this pin allows switching frequency synchronization of the device. The internal oscillator is clocked then by the frequency applied at the SYNC input. SI-Ground input. Ground connection for SI comparator resistor divider. Depending on SI_ENABLE this input is switched to high impedance or low ohmic to GND. Sense comparator input. Input of the low-battery comparator. This input is compared to an internal 1.25V reference where SO gives the result of the comparison. Can be used for any comparison, not necessarily as battery sense. Compensation input. Connect via RC-compensation network to GND. Sense comparator output. Open drain output from SI comparator at the adjustable version (TLE63892 GV), Pull down structure with an internal 20k pull up resistor to VOUT at the 5V version (TLE6389-2 GV50 and TLE6389-3 GV50).
1
2
FB
3
VOUT
4 5
GND SYNC
6
SI_GND
7
SI
8 9
COMP SO
Datasheet Rev. 2.1
4
2007-08-13
TLE 6389
Pin No 10
Symbol RO
Function Reset output. Open drain output from undervoltage reset comparator at the adjustable version (TLE6389-2 GV), Pull down structure with an internal 20k pull up resistor to VOUT at the 5V version (TLE6389-2 GV50 and TLE6389-3 GV50). Buck driver supply input. Connect a ceramic capacitor between BDS and VS to generate clamped gate-source voltage to supply the driver of the PMOS power stage. Gate drive output. Connect to the gate of the external P-Channel MOSFET. The voltage at GDRV swings between the levels of VS and BDS. Device supply input. Connect a 220nF ceramic cap close to the pin in addition to the low ESR tantalum input capacitance. Current-sense input. Connect current-sense resistor between VS and CS. The voltage drop over the sense-resistor determines the peak current flowing in the buck circuit. The external MOSFET is turned off when the peak current is exceeded.
11
BDS
12
GDRV
13
VS
14
CS
Datasheet Rev. 2.1
5
2007-08-13
TLE 6389
2 Item
Absolute Maximum Ratings Parameter Device supply input VS Symbol Limit Values Unit min. max. 61 - 61 - 61 V - V - V -0.3V < |VVS VGDRV| < 6.8V; -0.3V < |VBDS VGDRV| < 6.8V limited internally -0.3V < |VVS VBDS| < 6.8V |VVS - VCS| < 0.3V - Remarks
2.1 2.2 2.3 2.4 2.5
Voltage Current Current sense input CS Voltage Current Voltage
VVS IVS VCS ICS VGDRV
-0.3 - -0.3 - - 0.3
Gate drive output GDRV
2.6 2.7 2.8 2.9 2.10 2.11 2.12
Current Voltage Current Feedback input FB Voltage Current Voltage Current
IGDRV VBDS IBDS VFB IFB
- - 0.3 - - 0.3 -
- 61 - 6.8 - 61 -
- V - V - V -
Buck driver supply input BDS
Enable input SI_ENABLE VSI_ENAB - 0.3
LE
TLE6389-2 GV50, TLE6389-3 GV50
ISI_ENABL -
E
SI-Ground input SI_GND 2.13 2.14 2.15 2.16 Voltage Current Enable input ENABLE Voltage Current VENABLE IENABLE - 0.3 - 61 - V - TLE6389-2 GV VSI_GND ISI_GND - 0.3 - 61 - V -
Datasheet Rev. 2.1
6
2007-08-13
TLE 6389
2 Item
Absolute Maximum Ratings (cont'd) Parameter Symbol Limit Values Unit min. Sense comparator input SI max. 61 - 6.8 - 15 6.8 - 6.8 - 6.8 - 6.8 - 1.5 2 500 V - V - V V mA V mA V mA V mA kV kV V HBM1), pin VOUT HBM1), all pins except VOUT CDM2) limited internally limited internally TLE6389-2 GV TLE6389-2 GV50, TLE6389-3 GV50 Remarks
2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 2.25 2.26 2.27 2.28 2.29 2.30 2.31 2.32
Voltage Current Voltage Current Voltage Voltage Current Voltage Current Reset output RO Voltage Current Voltage Current ESD-Protection Electrostatic discharge voltage
VSI ISI VSO ISO VVOUT VVOUT IVOUT VCOMP ICOMP VRO IRO VSYNC ISYNC VESD VESD
- 0.3 - - 0.3 - - 0.3 - 0.3 - - 0.3 - - 0.3 - - 0.3 - -1.5 -2
Sense comparator output SO
Buck output voltage input VOUT
Compensation input COMP
Frequency synchronization input SYNC
VESDCDM -500
Datasheet Rev. 2.1
7
2007-08-13
TLE 6389
2 Item
Absolute Maximum Ratings (cont'd) Parameter Temperatures Symbol Limit Values Unit min. max. 150 150 C C - - Remarks
2.33 2.34
1) 2)
Junction temperature Storage temperature
Tj Tstg
-40 -50
ESD susceptibility HBM according to EIA/JESD 22-A 114B. ESD susceptibility CDM according to JESD 22-C101.
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation.
Datasheet Rev. 2.1
8
2007-08-13
TLE 6389
3 Item 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11
1)
Operating Range Parameter Supply voltage range Output voltage adjust range TLE 6389-2 GV Sense Resistor PMOS, on+off delay Buck driver supply capacitor Buck inductance Buck inductance Buck output capacitor Junction temperature Thermal Resistance Junction ambient Junction pin Rthj-a Rthj-p 140 50 K/W K/W Footprint only - Symbol VVS VOUT RSENSE ton+off
delay
Limit Values min. 5 7 10 220 47 22 100 - 40 max. 60 15 47 tmin300 1) 100 150
Unit V V m ns nF H H F C
Remarks
TLE 6389-2 GV Calculation see section 7 tmin= VVOUT/ (VVS*fSW)
CBDS L1 L1 COUT Tj
recommended value
A too high PMOS on+off delay might cause an instable output voltage
Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.
Datasheet Rev. 2.1
9
2007-08-13
TLE 6389
4
Electrical Characteristics
5V < VVS < 48V; -40C < Tj < 150 C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified
Item
Parameter
Symbol
Limit Values min. typ. max. 150 85
Unit
Test Condition
Current Consumption1) TLE6389-2 GV50 and TLE6389-3 GV50 4.1 4.2 Current IVS consumption of VS 80 70 A A VVS = 48V; PFM mode; VVS = 13.5V; PFM mode; Tj = 25 C VVS = 48V; VSI_ENABLE = 48V; PFM mode; VSI_ENABLE = L; VVOUT = 5.5V; VVS=13.5V; PFM mode; Tj = 25C VSI_ENABLE = H; VVOUT = 5.5V; VVS = 13.5V; VSI > VSI, high; PFM mode; VVS = 13.5V; VSI_ENABLE = H; VSI = 10V ; PFM mode;
4.3
Current consumption of SI_ENABLE Current consumption of VOUT
ISI_ENABL
E
9
30
A
4.4
IVOUT
95
130
A
4.5
140
220
A
4.6
Current consumption of SI
ISI
0.2
0.5
A
Datasheet Rev. 2.1
10
2007-08-13
TLE 6389
4
Electrical Characteristics (cont'd)
5V < VVS < 48V; -40C < Tj < 150 C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified
Item
Parameter
Symbol
Limit Values min. typ. max. 150
Unit
Test Condition
Current Consumption1) TLE6389-2 GV (variable) 4.7 Current IVS consumption of VS 80 A VVS = 48V; VENABLE = H; PFM mode; VOUT > 7V VVS = 13.5V; VENABLE = H; PFM mode; Tj = 25 C; VOUT > 7V VENABLE=0V; Tj < 105C VVS = 48V; VENABLE = H; PFM mode; VOUT = 8V; VVS = 13.5V; VENABLE = H; VSI > VSI, high; PFM mode; VVS = 13.5V; VENABLE = H; VSI = 10V ; PFM mode; Tj = 25C VVS = 13.5V; VFB = 1.25V; VENABLE = H; PFM mode; Tj = 25C
4.8
Current consumption of VS
70
85
A
4.9 4.10
Current consumption of VS Current consumption of ENABLE Current consumption of VOUT IEN 9
2 30
A A
4.11
IVOUT
140
220
A
4.12
Current consumption of SI
ISI
0.2
0.5
A
4.13
Current IFB consumption of FB
0.2
0.5
A
Datasheet Rev. 2.1
11
2007-08-13
TLE 6389
4
Electrical Characteristics (cont'd)
5V < VVS < 48V; -40C < Tj < 150 C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified
Item
Parameter Buck Controller
Symbol
Limit Values min. typ. max.
Unit
Test Condition
4.14
Output voltage
VVOUT
4.85
5.00 5.15
V
TLE6389-2 GV50, TLE6389-3 GV50; VVS=13.5V& 48V; PWM mode IOUT = 0.5 to 2A; RSENSE = 22m; RM1 = 0.25; RL1 = 0.1; TLE6389-2 GV50, TLE6389-3 GV50; VVS = 24V;PFM; IOUT = 15mA; RSENSE = 22m; RM1 = 0.25; RL1 = 0.1; TLE6389-3 GV50; VVS decreasing from 5.8V to 4.2V; ILOAD = 0mA to 500mA; RSENSE = 22m; RM1 = 0.4; RL1 = 0.1; TLE6389-2 GV TLE6389-2 GV; Calibrated divider, see section 7.3; VVS = 13.5V & 48V; IOUT = 0.5 to 2A; PWM Mode; RSENSE = 22m; RM1 = 0.25; RL1 = 0.1;
2007-08-13
4.15
4.75
5.00 5.25
V
4.16
3.8
V
4.17 4.18
FB threshold voltage Output voltage
VFB, th VVOUT
1.225 1.25 1.275 V 9.7 10.0 10.3 V
Datasheet Rev. 2.1
12
TLE 6389
4
Electrical Characteristics (cont'd)
5V < VVS < 48V; -40C < Tj < 150 C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified
Item 4.19
Parameter Output voltage
Symbol VVOUT
Limit Values min. typ. 9.5 max. 10.0 10.5
Unit V
Test Condition TLE6389-2 GV; Calibrated divider, see section 7.3; VVS = 24V; IOUT = 15mA; PFM Mode; RSENSE = 22m; RM1 = 0.25; RL1 = 0.1; TLE6389-2 GV, supplied by VS only, complete current to supply the IC drawn from VS, no reset function 2) TLE6389-2 GV, current to supply the IC drawn from VS and VOUT, as specified, 2) TLE6389-2 GV, PWM mode 2) TLE6389-2 GV, PFM mode 2)
4.20
Buck output voltage adjust range
VVOUT
VFB,
th
7
V
4.21
Buck output voltage adjust range
VVOUT
7
15
V
4.22
Buck output voltage accuracy Buck output voltage accuracy
VVOUT
0.97* VOUT
_nom
1.03* VOUT
_nom
4.23
VVOUT
0.95* VOUT
_nom
1.05* VOUT
_nom
Datasheet Rev. 2.1
13
2007-08-13
TLE 6389
4
Electrical Characteristics (cont'd)
5V < VVS < 48V; -40C < Tj < 150 C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified
Item 4.24
Parameter Line regulation
Symbol | VVOUT |
Limit Values min. typ. max. 35
Unit mV
Test Condition TLE6389-2 GV50, TLE6389-3 GV50, VVS = 9V to 16V; IOUT = 1A; RSENSE = 22m; PWM mode TLE6389-2 GV50, TLE6389-3 GV50, VVS = 16V to 32V; IOUT = 1A; RSENSE = 22m; PWM mode TLE6389-2 GV, VVS = 12V to 36V; VVOUT=10V IOUT = 1A; RSENSE = 22m; PWM mode
4.25
Line regulation
| VVOUT |
50
mV
4.26
Line regulation
VVOUT / VVOUT
2.5
%
Datasheet Rev. 2.1
14
2007-08-13
TLE 6389
4
Electrical Characteristics (cont'd)
5V < VVS < 48V; -40C < Tj < 150 C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified
Item 4.27
Parameter Load regulation
Symbol VVOUT / ILOAD
Limit Values min. typ. 40 max.
Unit mV/ A
Test Condition TLE6389-2 GV50, TLE6389-3 GV50, IOUT = 0.5A to 2A; VVS = 5.8V & 48V; RSENSE = 22m TLE6389-2 GV, IOUT = 0.5 to 2A; VVS= 13.5V & 48V; RSENSE = 22m VENABLE/SI_ENABLE =5V CBDS = 220 nF CGDRV = 4.7nF VENABLE/SI_ENABLE =5V CBDS = 220 nF CGDRV = 4.7nF3) Decreasing (VVSVBDS) until GDRV is permanently at VS level PMOS dependent;
2)
4.28
8* VOUT _nom/ V Gate driver, PMOS off VVS - VGDRV 0 0.2
mV/ A
4.29
V
4.30
Gate driver, PMOS on
VVS - VGDRV
6
8.2
V
4.31
Gate driver, UV lockout
VVS - VBDS
2.75
4
V
4.32
Gate driver, peak charging current Gate driver, peak discharging current Gate driver, gate voltage, rise time
IGDRV
1
A
4.33
IGDRV
1
A
PMOS dependent;
2)
4.34
tr
45
60
ns
VENABLE/SI_ENABLE =5V CBDS = 220 nF CGDRV = 4.7nF
Datasheet Rev. 2.1
15
2007-08-13
TLE 6389
4
Electrical Characteristics (cont'd)
5V < VVS < 48V; -40C < Tj < 150 C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified
Item 4.35
Parameter Gate driver, gate voltage, fall time Peak current limit threshold voltage Oscillator frequency Maximum duty cycle Minimum on time SYNC capture range
Symbol tf
Limit Values min. typ. 50 max. 65
Unit ns
Test Condition VENABLE/SI_ENABLE =5V CBDS = 220 nF CGDRV = 4.7nF
4.36
VLIM = VVS - VCS fOSC dMAX tMIN fsync
50
70
90
mV
4.37 4.38 4.39 4.40 4.41 4.42
290 100
360
420
kHz %
PWM mode only PWM mode only PWM mode only PWM mode only
2)
220 250 4.0
400 530
ns kHz V
SYNC trigger level VSYNC,h high SYNC trigger level low Reset Generator Reset threshold
0.8
V
2)
4.43 4.44 4.45
VVOUT, RT 3.5 4.5
3.65 3.8 4.65 4.8
V V mV
TLE6389-3 GV50; VVOUT decreasing TLE6389-3 GV50; VVOUT increasing TLE6389-2 GV50; VOUT(VS=6V, ILOAD=1A) -VVOUT,RT TLE6389-2 GV50; VVOUT increasing/ decreasing TLE6389-2 GV50
2)
Reset headroom
VRT,HEAD 80
4.46
Reset threshold
VVOUT, RT 4.5
4.65 4.8
V
4.47
Reset threshold hysteresis
VVOUT,
RT
50
mV
Datasheet Rev. 2.1
16
2007-08-13
TLE 6389
4
Electrical Characteristics (cont'd)
5V < VVS < 48V; -40C < Tj < 150 C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified
Item 4.48 4.49 4.50
Parameter Reset threshold
Symbol VFB, RT
Limit Values min. typ. 1.12 1.17 max.
Unit V V
Test Condition TLE6389-2 GV; VVOUT decreasing TLE6389-2 GV; VVOUT increasing TLE6389-2 GV50, TLE6389-3 GV50; Internally connected to VOUT TLE6389-2 GV50, TLE6389-3 GV50; IRO=0mA IRO, L=1mA; 2.5V < VVOUT < VRT IRO, L=0.2mA; 1V < VVOUT < 2.5V TLE6389-2 GV TLE6389-3 GV50 TLE6389-2 GV50
2)
Reset output pull up resistor
RRO
10
20
40
k
4.51
Reset output High voltage Reset output Low voltage Reset output Low voltage Reset delay time Reset delay time
VRO, H
0.8* VVOUT 0.2 0.2 17 70 21 82 0.4 0.4 25 100 10 VOUT _nom/ V +0.1 VFB,t /V +0.0 2
h_nom
V
4.52 4.53 4.54 4.55 4.56 4.57
VRO,L VRO,L trd trd
V V ms ms s V
Reset reaction time trr Overvoltage Lockout Overvoltage threshold VVOUT, OV
TLE6389-2 GV50, TLE6389-3 GV50; VVOUT increasing TLE6389-2 GV; VVOUT increasing
4.58
Overvoltage threshold
VFB, OV
V
Datasheet Rev. 2.1
17
2007-08-13
TLE 6389
4
Electrical Characteristics (cont'd)
5V < VVS < 48V; -40C < Tj < 150 C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified
Item
Parameter ENABLE Input
Symbol
Limit Values min. typ. max.
Unit
Test Condition
4.59 4.60
Enable ONthreshold Enable OFFthreshold SI_ENABLE Input Enable ONthreshold Enable OFFthreshold SI_GND Input Switch ON resistance Sense threshold Sense threshold Sense threshold hysteresis Sense output pull up resistor
VENABLE,
ON
4.5 0.8
V V
VENABLE,
OFF
4.61 4.62
VENABLE,
ON
4.5 0.8
V V
VENABLE,
OFF
4.63
RSW
50
100
230
VSI_ENABLE = 5V; ISI_GND = 3mA; VVS decreasing VVS increasing
Battery Voltage Sense 4.64 4.65 4.66 4.67 VSI, low VSI, high VSI, hys RSO 50 10 1.22 1.25 1.28 1.33 80 20 120 40 V V mV k TLE6389-2 GV50, TLE6389-3 GV50; Internally connected to VVOUT ISO,H =0mA ISO,L = 1mA; 2.5V < VVOUT; VSI < 1.13 V ISOL=0.2mA; 1V < VVOUT < 2.5V; VSI < 1.13 V
4.68 4.69
Sense out output High voltage Sense out output Low voltage
VSO,H VSO,L
0.8* VVOUT 0.2 0.4
V V
4.70
0.4
VVOUT V /V
Datasheet Rev. 2.1
18
2007-08-13
TLE 6389
4
Electrical Characteristics (cont'd)
5V < VVS < 48V; -40C < Tj < 150 C;
All voltages with respect to ground; positive current defined flowing into the pin; unless otherwise specified
Item
Parameter Thermal Shutdown
Symbol
Limit Values min. typ. max. 200
Unit
Test Condition
4.71
Thermal shutdown TjSD junction temperature Temperature hysteresis T
150
175
C
2)
4.72
1) 2) 3)
30
K
2)
The device current measurements for IVS and IFB exclude MOSFET driver currents. Not subject to production test - specified by design For 4V < VVS < 6V: VGDRV 0V.
Datasheet Rev. 2.1
19
2007-08-13
TLE 6389
5
Typical Performance Characteristics Current consumption IVOUT vs. temperature Tj at enabled device and VVOUT=5.5V
IVOUT A 180
Current consumption IVS vs. temperature Tj at enabled device and VVS=13.5V
IVS A 90
80
170
70
160
60
150
50
140
40
130
30
120
20 -50
-20
10
40
70
100
130
Tj C
160
110 -50
-20
10
40
70
100
130
Tj C
160
Current consumption IVS vs. temperature Tj at enabled device and VVS=48V
IVS A 110
Current consumption IVOUT vs. temperature Tj at enabled device and VVOUT=10V(-2GV)
IVOUT A 160
100
150
90
140
80
130
70
120
60
110
50
100
40 -50
-20
10
40
70
100
130
Tj C
160
90 -50
-20
10
40
70
100
130
Tj C
160
Datasheet Rev. 2.1
20
2007-08-13
TLE 6389
Internal oscillator frequency fOSC vs. temperature Tj
fOSC kHz 380
Peak current limit threshold voltage VLIM vs. temperature Tj
VLIM mV 110
370
100
360
90
350
80
340
70
330
60
320
50
310 -50
-20
10
40
70
100
130
Tj C
160
40 -50
-20
10
40
70
100
130
Tj C
160
Minimum on time tMIN (blanking) vs. temperature Tj
tMIN ns 350
Gate driver supply VVS - VBDS vs. temperature Tj
8.6 VVS-VBDS V 8.4
325
300
8.2
275
8.0
250
7.8
225
7.6
200
7.4
175 -50
-20
10
40
70
100
130
Tj C
160
7.2 -50
-20
10
40
70
100
130
Tj C
160
Datasheet Rev. 2.1
21
2007-08-13
TLE 6389
Output voltage VVOUT vs. temperature Tj in PFM mode (VVS=24V,ILoad=15mA,-3GV50)
5.15 VVOUT V 5.10
Lower Reset threshold VFB,RT vs. temperature Tj (-2GV)
VFB,RT V 1.14
1.13
5.05
1.12
5.00
1.11
4.95
1.10
4.90
1.09
4.85
1.08
4.80 -50
-20
10
40
70
100
130
Tj C
160
1.07 -50
-20
10
40
70
100
130
Tj C
160
Lower Reset threshold VVOUT, RT vs. temperature Tj (-3GV50)
3.72 VVOUT,RT V 3.70
Internal pull up resistors RRO and RSO vs. temperature Tj (-3GV50)
RRO k RSO k 45
40
3.68
35
3.66
30
3.64
25
3.62
20
3.60
15
3.58 -50
-20
10
40
70
100
130
Tj C
160
10 -50
-20
10
40
70
100
130
Tj C
160
Datasheet Rev. 2.1
22
2007-08-13
TLE 6389
Lower Sense threshold VSI, low vs. temperature Tj
VSI,low V 1.28
Output Voltage vs. Load Current, TLE6389-2 GV50
VOUT V 7
TLE 6389-2 GV50 RSENSE = 50m VVS = 13.5V App. Circuit Fig. 3
1.27
6
1.26
5
1.25
4
1.24
3
1.23
2
1.22
1
1.21 -50
0
-20 10 40 70 100 130 Tj C 160
0
0.25
0.5
0.75
1.0
1.25
1.5 1.75 ILOAD A
On resistance of SI_GND switch RSW vs. temperature Tj
RSW 280
Output Current vs. Load Current, TLE6389-3 GV50
VOUT V 7
TLE 6389-3 GV50 RSENSE = 50m VVS = 13.5V App. Circuit Fig. 3
240
6
200
5
160
4
120
3
80
2
40
1
0
-50
-20
10
40
70
100
130
Tj C
160
0
0
0.25
0.5
0.75
1.0
1.25
1.5 1.75 ILOAD A
Datasheet Rev. 2.1
23
2007-08-13
TLE 6389
Output Voltage vs Load Current
VOUT 1.4 VOUT,nom 1.2
TLE 6389-2 GV RSENSE = 50m VVS = 13.5V App. Circuit Fig. 3
1.0
0.8
0.6
0.4
0.2
0
0
0.25
0.5
0.75
1.0
1.25
1.5 1.75 ILOAD A
Datasheet Rev. 2.1
24
2007-08-13
TLE 6389
6
Detailed circuit description
In the following, some internal blocks of the TLE6389 are described in more detail. For the right choice of the external components please refer to the section application information. 6.1 PFM/PWM Step-down regulator
To meet the strict requirements in terms of current consumption demanded by all Bodyand 42V PowerNet applications a special PFM (Pulse Frequency Modulation) - PWM (Pulse Width Modulation) control scheme for highest efficiency is implemented in the TLE 6389 regulators. Under light load conditions the output voltage is able to increase slightly and at a certain threshold the controller jumps into PFM mode. In this PFM operation the PMOS is triggered with a certain on time (depending on input voltage, output voltage, inductance- and sense resistor value) whenever the buck output voltage decreases to the so called WAKE-threshold. The switching frequency of the step down regulator is determined in the PFM mode by the load current. It increases with increasing load current and turns finally to the fixed PWM frequency at a certain load current depending on the input voltage, current sense resistor and inductance. The diagram below shows the buck regulation circuit of the TLE 6389 .
VS + -
CS
VFB, OV + -
VREF
VREF + -
VDIODE
Currentsense Amplifier
OverVoltage Lockout
OverTemp. Shutdown
VS
Blanking
VREF + VFB
+
Error Amplifier PWM Comparator WakeComparator
PFM
>1
R S Q
&
GDRV
Levelshift
BDS
Slopecompensation
VREF
+ -
VFB, WK
MUX
PWM
SYNC MODE
Oscillator
Figure 1
Buck control scheme
The TLE 6389 uses a slope-compensated peak current mode PWM control scheme in which the feedback or output voltage of the step down circuit and the peak current of the current through the PMOS are compared to form the OFF signal for the external PMOS.
Datasheet Rev. 2.1 25 2007-08-13
TLE 6389
The ON-trigger is set periodically by the internal oscillator when acting in PWM mode and is given by the output of the WAKE-comparator when operating in PFM mode. The Multiplexer (MUX) is switched by the output of the MODE-detector which distinguishes between PFM and PWM by tracking the output voltage (goto PFM) and by tracking the gate trigger frequency (goto PWM). In PFM mode the peak current limit is reduced to prevent overshoots at the output of the buck regulator. In order to avoid a gate turn off signal due to the current peak caused by the parasitic capacitance of the catch diode the blanking filter is necessary. The blanking time is set internally to 200ns and determines (together with the PMOS turn on and turn off delay) the minimum duty cycle of the device. In addition to the PFM/PWM regulation scheme an overvoltage lockout and thermal protection are implemented to guarantee safe operation of the device and of the supplied application circuit.
6.2
Battery voltage sense
To detect undervoltage conditions at the battery a sense comparator block is available within the TLE 6389. The voltage at the SI input is compared to an internal reference of typ. 1.25V. The output of the comparator drives a NMOS structure giving a low signal at SO as soon as the voltage at SI decreases below this threshold. In the 5V fixed version an internal pull up resistor is connected from the drain of the NMOS to the output of the buck converter, in the variable version SO is open drain. The sense in voltage divider can be switched to high impedance by a low signal at the SI_ENABLE to avoid high current consumption to GND (TLE6389-2 GV50 and TLE6389-3 GV50 only). Of course the sense comparator can be used for any input voltage and does not have to be used for the battery voltage sense only.
6.3
Undervoltage Reset
The output voltage is monitored continuously by the internal undervoltage reset comparator. As soon as the output voltage decreases below the thresholds given in the characteristics the NPN structure pulls RO low (latched). In the 5V fixed version an internal pull up resistor is connected from the collector of the NPN to the output of the buck converter, in the variable version RO is open collector. At power up RO is kept low until the output voltage has reached its reset threshold and stayed above this threshold for the power on reset delay time.
Datasheet Rev. 2.1
26
2007-08-13
TLE 6389
7
Application information
Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. 7.1 General
The TLE 6389 step-down DC-DC controllers are designed primarily for use in Automotive applications where high input voltage range requirements have to be met. Using an external P-MOSFET and current-sense resistor allows design flexibility and the improved efficiencies associated with high-performance P-channel MOSFETs. The unique, peak current-limited, PWM/PFM control scheme gives these devices excellent efficiency over wide load ranges, while drawing around 100A current from the battery under no load condition. This wide dynamic range optimizes the TLE 6389 for automotive applications, where load currents can vary considerably as individual circuit blocks are turned on and off to conserve energy. Operation to a 100% duty cycle allows the lowest possible dropout voltage, maintaining operation during cold cranking. High switching frequencies and a simple circuit topology minimize PC board area and component costs. 7.2 Typical application circuits
Note: These are very simplified examples of an application circuit. The function must be verified in the real application
.
VIN
RSENSE= 47m
M1
L1 = 47 H
V OUT IOUT
C IN1 = 100 F
C BDS= 220 nF
11 BDS VS 7 SI SI_GND 6 14 CS 12 GDRV 2
D1
COUT = 100 F M1: Infineon BSO613SPV Infineon BSP613P D1: Motorola MBRD360 L1: EPCOS B82479-A1473-M Coilcraft DO3340P-473 CIN1: Electrolythic CIN2: Ceramic COUT: Low ESR Tantalum
13
RSI1= 400k RSI2= 100k
CIN2 = 220nF
TLE6389-2 GV50 TLE6389-3 GV50
SI_ENABLE 1 ON OFF SYNC 5 GND 4
3 FB VOUT 9 SO 8 COMP RO 10
2.2nF 680
Figure 2
Application circuit TLE6389-2 GV50 and TLE6389-3 GV50
Datasheet Rev. 2.1
27
2007-08-13
TLE 6389
VIN
RSENSE= 47m
M1
L1 = 47 H
V OUT
C IN1 = 100 F
to e.g. 5V rail C BDS= 220 nF
11 13 BDS VS 14 CS 12 GDRV 3 VOUT SO FB COMP SYNC 5 GND 4 RO 10 9 2 8
D1
RSO= RRO= 20k
COUT = 100 F RFB1= 330k M1: Infineon BSO613SPV Infineon BSP613P D1: Motorola MBRD360 L1: EPCOS B82479-A1473-M Coilcraft DO3340P-473 CIN1: Electrolythic CIN2: Ceramic COUT: Low ESR Tantalum
RSI1= 400k RSI2= 100k
CIN2 = 220nF
7
TLE6389-2 GV
SI SI_GND ENABLE 6 1 ON OFF
to C 2.2nF 680 to C RFB2= 47k
Figure 3
Application circuit TLE6389-2 GV
7.3
Output voltage at adjustable version - feedback divider
The output voltage is sensed either by an internal voltage divider connected to the VOUT pin (TLE6389-2 GV50 and TLE6389-3 GV50, fixed 5V versions) or an external divider from the Buck output voltage to the FB pin (TLE6389-2 GV, adjustable version). Pin VOUT has to be connected always to the Buck converter output regardless of the selected output voltage for the -2GV version. To determine the resistors of the feedback divider for the desired output voltage VOUT at the TLE6389-2 GV select RFB2 between 5k and 500k and obtain RFB1 with the following formula: V OUT R FB1 = R FB2 ---------------- - 1 V FB, th VFB is the threshold of the error amplifier with its value of typical 1.25V which shows that the output voltage can be adjusted in a range from 1.25V to 15V. However the integrated Reset function will only be operational if the output voltage level is adjusted to >7V. Also the current consumption will be increased in PFM mode in the range between 1.25V and 7V.
Datasheet Rev. 2.1 28 2007-08-13
TLE 6389
7.4
SI_Enable
Connecting SI_ENABLE to 5V causes SI_GND to have low impedance. Thus the SI comparator is in operation and can be used to monitor the battery voltage. SO output signal is valid. Connecting SI_ENABLE to GND causes SI_GND to have high impedance. Thus the SI comparator is not able to monitor the battery voltage. SO output signal is invalid.
7.5
Battery sense comparator - voltage divider
The formula to calculate the resistor divider for the sense comparator is basically the same as for the feedback divider in section before. With the selected resistor RSI2, the desired threshold of the input voltage VIN, UV and the lower sense threshold VSI, low the resistor RSI1 is given to: V IN, UV R SI1 = R SI2 ------------------ - 1 V SI, low
For high accuracy and low ohmic resistor divider values the On-resistance of the SI_GND NMOS (typ. 100) has to be added to RSI2.
7.6
Undervoltage reset - delay time
The diagram below shows the typical behavior of the reset output in dependency on the input voltage VIN, the output voltage VVOUT or VFB.
Datasheet Rev. 2.1
29
2007-08-13
TLE 6389
VIN
VVOUT VFB
trr
< trr
t
VVOUT, RT VFB,RT
t
VRO
trd
trd
trd
trd
t
thermal shutdown under voltage over load
Figure 4 7.7
Reset timing 100% duty-cycle operation and dropout
The TLE 6389 operates with a duty cycle up to 100%. This feature allows to operate with the lowest possible drop voltage at low battery voltage as it occurs at cold cranking. The MOSFET is turned on continuously when the supply voltage approaches the output voltage level, conventional switching regulators with less than 100% duty cycle would fail in that case. The drop- or dropout voltage is defined as the difference between the input and output voltage levels when the input is low enough to drop the output out of regulation. Dropout depends on the MOSFET drain-to-source on-resistance, the current-sense resistor and the inductor series resistance. It is proportional to the load current:
V drop = I LOAD ( R DS ( ON )PMOS + R SENSE + R INDUCTANCE )
Datasheet Rev. 2.1
30
2007-08-13
TLE 6389
7.8
SYNC Input and Frequency Control
The TLE 6389's internal oscillator is set for a fixed PWM switching frequency of 360kHz or can be synchronized to an external clock at the SYNC pin. When the internal clock is used SYNC has to be connected to GND. SYNC is a negative-edge triggered input that allows synchronization to an external frequency ranging between 270kHz and 530kHz. When SYNC is clocked by an external signal, the converter operates in PWM mode until the load current drops below the PWM to PFM threshold. Thereafter the converter continues operation in PFM mode.
7.9
Shutdown Mode
Connecting ENABLE to GND places the TLE6389-2 GV in shutdown mode. In shutdown, the reference, control circuitry, external switching MOSFET, and the oscillator are turned off and the output falls to 0V. Connect ENABLE to voltages higher than 4.5V for normal operation. As this input operates analog the voltage applied at this pin should have a slope of 0.5V/3s to avoid undefined states within the device.
7.10
Buck converter circuit
A typical choice of external components for the buck converter circuit is given in figure 2 and 3. For basic operation of the buck converter the input capacitors CIN1, CIN2, the driver supply capacitor CBDS, the sense resistor RSENSE, the PMOS device, the catch diode D1, the inductance L1 and the output capacitor COUT are necessary. In addition for low electromagnetic emission a Pi-filter at the input and/or a small resistor in the path between GDRV and the gate of the PMOS may be necessary. 7.10.1 Buck inductance (L1) selection in terms of ripple current:
The internal PWM/PFM control loop includes a slope compensation for stable operation in PWM mode. This slope compensation is optimized for inductance values of 47H and Sense resistor values of 47m for the 5V output voltage versions. When choosing an inductance different from 47H the Sense resistor has to be changed also: R SENSE 3 ------------------- = (0,5...1,0 ) x10 --H L1 Increasing this ratio above 1000 /H may result in sub harmonic oscillations as wellknown for peak current mode regulators without integrated slope compensation.
Datasheet Rev. 2.1
31
2007-08-13
TLE 6389
To achieve the same effect of slope compensation in the adjustable voltage version also the inductance in H is given by
-4 H H 2,0 x 10 - 4 -------- V -------OUT R SENSE < L1 < 4,0 x 10 V V OUT R SENSE V
The inductance value determines together with the input voltage, the output voltage and the switching frequency the current ripple which occurs during normal operation of the step down converter. This current ripple is important for the all over ripple at the output of the switching converter. ( V IN - V OUT ) V OUT I = -----------------------------------------------------f SW V IN L1
In this equation fsw is the actual switching frequency of the device, given either by the internal oscillator or by an external source connected to the SYNC pin. When picking finally the inductance of a certain supplier (Epcos, Coilcraft etc.) the saturation current has to be considered. The saturation current value of the desired inductance has to be higher than the maximum peak current which can appear in the actual application. 7.10.2 Determining the current limit
The peak current which the buck converter is able to provide is determined by the peak current limit threshold voltage VLIM and the sense resistor RSENSE. With a maximum peak current given by the application (IPEAK, PWM=ILOAD+0.5I) the sense resistor is calculated to V LIM R SENSE = -----------------------------------2 I PEAK, PWM
The equation above takes account for the foldback characteristic of the current limit as shown in the Fig. 'Output Voltage vs. Load Current' on page 24/25 by introducing a factor of 2. It must be assured by correct dimensioning of RSENSE that the load current doesn't reach the foldback part of the characteristic curve.
Datasheet Rev. 2.1
32
2007-08-13
TLE 6389
7.10.3
PFM and PWM thresholds
The crossover thresholds PFM to PWM and vice versa strongly depend on the input voltage VIN, the Buck converter inductance L1, the sense resistor value RSENSE and the turn on and turn off delays of the external PMOS. For more details on the PFM to PWM and PWM to PFM thresholds please refer to the application note "TLE6389 - Determining PFM/PWM current thresholds". 7.10.4 Buck output capacitor (COUT) selection:
The choice of the output capacitor effects straight to the minimum achievable ripple which is seen at the output of the buck converter. In continuous conduction mode the ripple of the output voltage can be estimated by the following equation:
1 V Ripple = I R ESRCOUT + ----------------------------------- 8f C
SW OUT
From the formula it is recognized that the ESR has a big influence in the total ripple at the output, so low ESR tantalum capacitors are recommended for the application. One other important thing to note are the requirements for the resonant frequency of the output LC-combination. The choice of the components L and C have to meet also the specified range given in section 3 otherwise instabilities of the regulation loop might occur. 7.10.5 Input capacitor (CIN1) selection:
At high load currents, where the current through the inductance flows continuously, the input capacitor is exposed to a square wave current with its duty cycle VOUT/VI. To prevent a high ripple to the battery line a capacitor with low ESR should be used. The maximum RMS current which the capacitor has to withstand is calculated to:
2 V OUT 1 I I RMS = I LOAD -------------- 1 + -- ----------------------- 3 2 I LOAD V IN
For low ESR an e.g. Al-electrolytic capacitance in parallel to an ceramic capacitance could be used.
Datasheet Rev. 2.1
33
2007-08-13
TLE 6389
7.10.6
Freewheeling diode / catch diode (D1)
For lowest power loss in the freewheeling path Schottky diodes are recommended. With those types the reverse recovery charge is negligible and a fast hand over from freewheeling to forward conduction mode is possible. Depending on the application (12V battery systems) 40V types could be also used instead of the 60V diodes. Also for high temperature operation select a Schottky-diode with low reverse leakage. A fast recovery diode with recovery times in the range of 30ns can be also used if smaller junction capacitance values (smaller spikes) are desired. 7.10.7 Buck driver supply capacitor (CBDS)
The voltage at the ceramic capacitor is clamped internally to 7V, a ceramic type with a minimum of 220nF and voltage class 16V would be sufficient. 7.10.8 Input pi-filter components for reduced EME
At the input of Buck converters a square wave current is observed causing electromagnetical interference on the battery line. The emission to the battery line consists on one hand of components of the switching frequency (fundamental wave) and its harmonics and on the other hand of the high frequency components derived from the current slope. For proper attenuation of those interferers a -type input filter structure is recommended which is built up with inductive and capacitive components in addition to the Input caps CIN1 and CIN2. The inductance can be chosen up to the value of the Buck converter inductance, higher values might not be necessary, the additional capacitance should be a ceramic type in the range up to 100nF. Inexpensive input filters show due to their parasitrics a notch filter characteristic, which means basically that the low pass filter acts from a certain frequency as a high pass filter and means further that the high frequency components are not attenuated properly. To slower down the slopes at the gate of the PMOS switch and get down the emission in the high frequency range a small gate resistor can be put between GDRV and the PMOS gate. 7.10.9 Frequency compensation
The external frequency compensation pin should be connected via a 2.2nF (>10V) ceramic capacitor and a 680 (1/8W) resistor to GND. This node should be kept free from switching noise.
Datasheet Rev. 2.1
34
2007-08-13
TLE 6389
7.11 Device CIN1 CIN2 L1
Components recommendation - overview Type Electrolytic /Foil type Ceramic B82464-A4473 B82479-A1473-M DO3340P-473 DO5022P-683 DS5022P-473 Supplier various various EPCOS EPCOS Coilcraft Coilcraft Coilcraft Infineon Infineon Infineon various Motorola Motorola various EPCOS various Remark 100F, 60V 220nF, 60V 47H, 1.6A, 145m 47H, 3.5A, 47m 47H, 3.8A, 110m 68H, 3.5A, 130m 47H, 4.0A, 97m 60V, 3.44A, 130m, NL 60V, 2.9A, 130m, NL 60V, 9A, 250m, LL 220nF, 16V Schottky, 60V, 3A Schottky, 40V, 3A Schottky, 40V, 3A Low ESR Tantalum, 100F, 10V see 7.10.9.
M1
BSO 613SPV BSP 613P SPD09P06PL
CBDS D1
Ceramic MBRD360 MBRD340 SS34
COUT CCOMP 7.12
B45197-A2107 Ceramic
Layout recommendation
The most sensitive points for Buck converters - when considering the layout - are the nodes at the input, output and the gate of the PMOS transistor and the feedback path. For proper operation and to avoid stray inductance paths the external catch diode, the Buck inductance and the input capacitor CIN1 have to be connected as close as possible to the PMOS device. Also the GDRV path from the controller to the MosFet has to be as short as possible. Best suitable for the connection of the cathode of the catch diode and one terminal of the inductance would be a small plain located next to the drain of the PMOS. The GND connection of the catch diode must be also as short as possible. In general the GND level should be implemented as surface area over the whole PCB as second layer, if necessary as third layer. The feedback path has to be well grounded also, a ceramic capacitance might help in addition to the output cap to avoid spikes. To obtain the optimum filter capability of the input pi-filter it has to be located also as close as possible to the input. To filter the supply input of the device (VS) the ceramic cap should be connected directly to the pin. As a guideline an EMC optimized application board / layout is available.
Datasheet Rev. 2.1 35 2007-08-13
TLE 6389
8
Package Outlines
0.35 x 45
1.75 MAX.
0.175 0.07 (1.47)
C
4 -0.2
1.27 0.41+0.10 2) -0.06 14
B
0.1
0.2 M A B 14x
8 60.2
0.64 0.25
0.2 M C
1 7 1) 8.75 -0.2
A
Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area
GPS01230
8MAX.
Dimensions in mm
1)
Figure 5
Outline PG-DSO-14-1 (Plastic Green Dual Small Outline)
Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Datasheet Rev. 2.1
36
0.19 +0.06
2007-08-13
TLE 6389
9 Version Rev. 2.0 Rev. 2.1
Revision History Date Changes
2006-08-24 Final Datasheet TLE 6389-2/-3 2007-08-13 Initial version of RoHS-compliant derivate of TLE 6389-2/-3 - page 1: AEC certified statement added - page 1 and page 36: RoHS compliance statement and green product feature added - page 1 and page 36: Package changed to RoHS compliant version - Legal Disclaimer updated
Datasheet Rev. 2.1
37
2007-08-13
Edition 2007-08-13 Published by Infineon Technologies AG 81726 Munich, Germany
(c) 2007 Infineon Technologies AG All Rights Reserved.
Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

▲Up To Search▲

Price & Availability of TLE638907

	To Download TLE638907 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .